The impact of atomic layer deposited SiO₂ passivation for high-k Ta_1−xZr_xO on the InP substrate

Background

III–V semiconductors such as InP offer higher electron mobility than Si, but high-k oxides on III–V substrates form defective interfaces with a high interface trap density (Dit) that pins the Fermi level. Ta2O5 has a high dielectric constant but suffers from poor thermal stability and oxygen-vacancy defects, and In diffusing through the high-k layer during deposition or annealing degrades device performance. Earlier passivation approaches did not prevent native oxide growth during annealing or effectively reduce Dit.

Design and approach

The study combined two measures. Zr was incorporated into Ta2O5 by an ALD supercycle (one ZrO2 cycle per eight Ta2O5 cycles at 250 °C), giving a Ta : Zr ratio of 3 : 2, to compensate oxygen vacancies. An ALD SiO2 interlayer of 5 or 10 cycles was then inserted between the dielectric and the InP to control interfacial layer growth. Si-doped (100) n-InP (3–5 × 10^17 cm−3) was treated in 1% hydrofluoric acid and 21% (NH4)2S before deposition, the stacks received a post-deposition anneal in N2 at 500 °C for 20 s, and TaN served as the gate electrode.

How it was evaluated

Ta1−xZrxO/InP capacitors without SiO2 were compared with Ta1−xZrxO/SiO2/InP capacitors. Interfaces were examined by cross-sectional high-resolution transmission electron microscopy (HR-TEM) with energy-dispersive X-ray spectroscopy (EDS), and by X-ray photoelectron spectroscopy (XPS) of the In 3d5/2, P 2p and Si 2p core levels combined with Ar sputtering for depth profiling, before and after annealing. Electrical behaviour was assessed by multi-frequency capacitance–voltage (C–V) measurements, normalized parallel conductance maps and leakage current measurements swept from 0 to 3.5 MV cm−1.

Key results

Without SiO2, the 9.2 nm gate stack consisted of 6.5 nm of Ta1−xZrxO over a 2.7 nm interfacial layer, and EDS showed that Zr incorporation alone did not stop In diffusion into the dielectric. The film remained insulating and thermally stable after annealing at 500 °C, with no notable increase in interfacial oxidation. With the SiO2 interlayer, the Ta1−xZrxO thickness was retained while the interlayer thickness decreased significantly, which the authors suggest may be because oxygen from the In/P oxides bonds to Si. XPS identified an In/P–O–Si silicate component, Si 2p spectra confirmed Si–O bonding, and P 2p spectra indicated negligible P diffusion into the dielectric.

The unpassivated stack gave a capacitance equivalent thickness (CET) of 1.8 nm at 100 Hz and a dielectric constant of about 20, but its flatband voltage was about 570 mV, which the authors relate to In diffusion, and the conductance map showed no clear peak, indicating Fermi-level pinning. With SiO2, accumulation dispersion fell from 21.1% to 11.3% (100 Hz–100 kHz), the flatband voltage decreased, the minimum inversion capacitance at 1 MHz approached the ideal value, and lower, narrower conductance peaks indicated a lower Dit. The Dit at 0.27 eV near the conduction band was 4 × 10^12 cm−2 eV−1 for the passivated stack; for the unpassivated stack qDit exceeded Cox, so the conductance method could overestimate Dit by an order of magnitude and the authors considered a reliable value difficult to extract in the same way.

Leakage at 1 MV cm−1 decreased from 3.2 × 10−10 without SiO2 to 8.2 × 10−12 and 8.3 × 10−13 with 5 and 10 SiO2 cycles (the text prints the unit as Å), and leakage decreased as the SiO2 thickness increased. Without SiO2, conduction was dominated by trap-assisted Poole–Frenkel (P–F) tunnelling, whereas the passivated capacitors showed trap-assisted or P–F tunnelling below 0.75 MV cm−1 (5 cycles) or 1.2 MV cm−1 (10 cycles) and Fowler–Nordheim (F–N) tunnelling above these fields.

Open questions

The authors note that the effective dielectric constant decreases after SiO2 passivation and regard this as an acceptable trade-off for the improved electrical behaviour. They also state that the origin of the stronger P-oxide signal in the passivated stack after longer sputtering remained uncertain.

How it connects to other research

The related review by Clark, cited in this paper, surveys high-k dielectrics and ALD for CMOS and memory devices, whereas this study addresses a specific interface problem on InP, In out-diffusion and Fermi-level pinning under a Zr-doped Ta2O5 dielectric, with an ALD SiO2 interlayer.