Bridging IC chips and deformable circuits: A packaging framework for high-density soft electronics

Background

Soft electronics are moving from single-function sensors to body-conformal systems with on-board processing, memory and wireless communication. Stretchable substrates, electrodes, interconnects, passive components and transistors have advanced, but deformable transistor arrays listed in the review reach densities far below those of silicon chips, so IC chips remain necessary for system control and power management. Their rigidity, thickness and dense input/output (I/O) pads concentrate stress at the chip periphery, thermal history adds residual and cyclic stress, and connecting many pads in a small footprint without shorts is difficult within the narrow processing window of soft circuits.

How the review is organized

The review first classifies architectures by where rigid chips sit relative to the deformable substrate and shows that, as conformity increases, the main bottleneck moves from rigid-core stiffness to the rigid-to-soft interconnect and then to the chip-mounting region. It then analyzes packaging design along three axes. Adhesion is treated as forming a continuous interface through intimate contact and interfacial coupling, with bonding mechanisms ordered by length scale from chemical bonding to mechanical adhesion. Electrical design is divided into electronic junctions, ionic interfaces and mixed ionic-electronic interfaces, plus signal integrity at fine pitch. Stress management covers structural, material and thermal approaches.

Scope of the review

Tables 2–4 compare soft-encapsulated PCB, hybrid and fully stretchable systems by function, integration strategy, maximum strain, cyclic test, channel count, package pin count, minimum pitch, process temperature and technology readiness level (TRL). Table 5 summarizes chip location, interface type, stretchability, integration density and main challenge for each architecture. Table 6 lists thermal conductivity and coefficient of thermal expansion (CTE) of polymers, metals and silicon, and Table 7 compares chip-integration methods (embedding, direct wiring, interposer and anisotropic conductive adhesive) by chip type, maximum strain, cyclic test and minimum pad spacing. The review notes that maximum strains in these tables are generally single-loading values.

Main points of the review

Architectures: soft-encapsulated PCBs reach high functional density and TRL of 5–6 or higher; one cited infant sensor placed sensing, memory, power management and wireless chips in a 17 mm × 30 mm footprint, but the rigid core limits stretchability. Hybrid systems soften only the tissue-facing electrodes, which shifts the challenge to rigid-to-soft interconnects, where conventional anisotropic conductive films (ACFs) need bonding above 140 °C and 18 kg cm−2 and can drift in contact resistance on soft polymers. Fully stretchable systems, such as a cited liquid-metal PCB tolerating over 200% strain, currently integrate chips with few pads, and adhesive mounting regions stiffen the area around the chip.

Interfaces and stress: the review argues that interfacial stability, rather than bulk resistance, is the primary electrical reliability metric. In a cited example, a single-walled carbon nanotube barrier kept the initial contact resistance of a liquid-metal/silver junction under repeated 30% stretching, whereas the unprotected junction rose by 70% after 3000 cycles. At fine pitch, fewer conductive particles per pad and capacitive coupling between dense traces threaten signal integrity. Structural buffers, intermediate-modulus interlayers and graded-modulus substrates redistribute stress, and the large CTE gap between polymers (for example 300 ppm/K for PDMS) and silicon (1 ppm/K) links thermal cycling to edge delamination in bonded assemblies.

Packaging strategies: for rigid-to-soft interconnection, self-adhesive liquid-metal or Au/SEBS interconnects simplify assembly but are limited to about 100 μm features, whereas stretchable ACFs reached anisotropic conduction at gaps near 10 μm. For chip bonding, Table 7 spans minimum pad spacings from 600 μm to below 10 μm; embedding, direct wiring, interposers and anisotropic conductive adhesives each trade process damage, shorting risk, rigid footprint or filler control. An interposer approach survived over 700% failure strain, but the authors stress that cyclic fatigue at physiological strains below 30% governs real lifetime.

Design framework: Figure 14 begins with target tissue and device function. Tissue compliance sets electrode requirements, and functional complexity sets I/O density; low deformability favors soft-encapsulated PCBs, compliant interfaces with dense circuits favor hybrid designs, and full conformability requires fully stretchable electronics with chip-level bonding. The framework then calls for evaluation in the operating environment, including encapsulation of chip edges and fine pitch feedthroughs with organic/inorganic multilayers or local overmolding.

Open questions

The authors conclude that many packaging approaches do not scale to sub-100 μm pitch, where smaller contacts raise open- and short-circuit risk and closer spacing increases parasitic capacitance and crosstalk. Junction integrity under cyclic stretching, bending and twisting remains difficult even after successful initial bonding, many demonstrations use chips with few pads, and higher interconnect density usually reduces stretchability. They call for fine pitch packaging that is stable under cyclic deformation and compatible with diverse materials and processes.

How it connects to other research

The solution-processed liquid-metal conductors reported in npj Flexible Electronics (DOI 10.1038/s41528-021-00123-x) integrated LED chips with liquid-metal interconnects, a few-pad case of chip mounting; this review addresses the further step of bonding high-pin-count ICs at fine pitch, where shorting, isolation and cyclic contact stability become limiting.